Programmable neural logic

Circuits of threshold elements (Boolean input, Boolean output neurons) have been shown to be surprisingly powerful. Useful functions such as XOR, ADD and MULTIPLY can be implemented by such circuits more efficiently than by traditional AND/OR circuits. In view of that, we have designed and built a programmable threshold element. The weights are stored on polysilicon floating gates, providing long-term retention without refresh. The weight value is increased using tunneling and decreased via hot electron injection. A weight is stored on a single transistor allowing the development of dense arrays of threshold elements. A 16-input programmable neuron was fabricated in the standard 2 μm double-poly, analog process available from MOSIS. We also designed and fabricated the multiple threshold element introduced in [5]. It presents the advantage of reducing the area of the layout from O(n^2) to O(n); (n being the number of variables) for a broad class of Boolean functions, in particular symmetric Boolean functions such as PARITY. A long term goal of this research is to incorporate programmable single/multiple threshold elements, as building blocks in field programmable gate arrays

Impact Ionization and Hot-Electron Injection Derived Consistently from Boltzmann Transport

We develop a quantitative model of the impact-ionizationand hot-electron–injection processes in MOS devices from first principles. We begin by modeling hot-electron transport in the drain-to-channel depletion region using the spatially varying Boltzmann transport equation, and we analytically find a self consistent distribution function in a two step process. From the electron distribution function, we calculate the probabilities of impact ionization and hot-electron injection as functions of channel current, drain voltage, and floating-gate voltage. We compare our analytical model results to measurements in long-channel devices. The model simultaneously fits both the hot-electron- injection and impact-ionization data. These analytical results yield an energydependent impact-ionization collision rate that is consistent with numerically calculated collision rates reported in the literature

Neutrophil NETs: a novel contributor to preeclampsia-associated placental hypoxia?

Recent studies have suggested that the innate immune system is involved in the pathogenesis of preeclampsia. Its pathogenesis involves neutrophil activation and increased levels of cell-free DNA in the maternal plasma. Activation of neutrophils has recently been shown to induce DNA containing neutrophil extracellular traps (NETs) which trap and kill bacteria. Massive NETs induction by the placentally derived factors (IL-8 and placental micro-debris) and their increased presence in preeclamptic placenta suggest that NETs might be involved in the pathogenesis of preeclampsia. Therefore, increased presence of NETs in preeclampsia may play a role in the deficient placental perfusion associated with this disorde

Floating-Gate MOS Synapse Transistors

Our goal is to develop silicon learning systems. One impediment to achieving this goal has been the lack of a simple circuit element combining nonvolatile analog memory storage with locally computed memory updates. Existing circuits [63, 132] typically are large and complex; the nonvolatile floating-gate devices, such as EEPROM transistors. typically are optimized for binary-valued storage [17], and do not compute their own memory updates. Although floating-gate transistors can provide nonvolatile analog storage [1, 15], because writing the memory entails the difficult process of moving electrons through Si0_2, these devices have not seen wide use as memory elements in silicon learning systems

The matching of small capacitors for analog VLSI

The capacitor has become the dominant passive component for analog circuits designed in standard CMOS processes. Thus, capacitor matching is a primary factor in determining the precision of many analog circuit techniques. In this paper, we present experimental measurements of the mismatch between square capacitors ranging in size from 6 μm×6 μm to 20 μm×20 μm fabricated in a standard 2 μm double-poly CMOS process available through MOSIS. For a size of 6 μm×6 μm, we have found that those capacitors that fell within one standard deviation of the mean matched to better than 1%. For the 20 μm×20 μm size, we observed that those capacitors that fell within 1 standard deviation of the mean matched to about 0.2%. Finally, we observed the effect of nonidentical surrounds on capacitor matching

An Adaptive WTA using Floating Gate Technology

We have designed, fabricated, and tested an adaptive Winner-Take-All (WTA) circuit based upon the classic WTA of Lazzaro, et al [1]. We have added a time dimension (adaptation) to this circuit to make the input derivative an important factor in winner selection. To accomplish this, we have modified the classic WTA circuit by adding floating gate transistors which slowly null their inputs over time. We present a simplified analysis and experimental data of this adaptive WTA fabricated in a standard CMOS 2µm process

Application performance of elements in a floating–gate FPAA

Field–programmable analog arrays (FPAAs) provide a method for rapidly prototyping analog systems. Currently available commercial and academic FPAAs are typically based on operational amplifiers (or other similar analog primitives) with only a few computational elements per chip. While their specific architectures vary, their small sizes and often restrictive interconnect designs leave current FPAAs limited in functionality, flexibility, and usefulness. In this paper, we explore the use of floating–gate devices as the core programmable element in a signal processing FPAA. A generic FPAA architecture is presented that offers increased functionality and flexibility in realizing analog systems. In addition, the computational analog elements are shown to be widely and accurately programmable while remaining small in area. 1. LOW–POWER SIGNAL PROCESSING The future of FPAAs lie in their ability to speed the implementatio